CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate devices, resulting in increased bitline (BL) and wordline (WL) capacitances (
${C}_{\text {BL}}$
and
${C}_{\text {WL}}$
) compared to nonstacked SRAMs. Previous research has reported that the higher parasitic capacitance hinders the power and performance gains between nodes. In this work, as a hypothetical device option aside from sequential and monolithic CFET, hybrid CFET is introduced in SRAM design with the features of double-sided interconnect design in 3-Å-compatible technology (A3). To assess its potential value in future SRAM roadmap, a comprehensive design technology co-optimization (DTCO) “what-if analysis” has been conducted. Hybrid CFET enables relaxation of metal width and shorter via connections in SRAM design compared to previous approaches. Therefore, A3 hybrid CFET SRAM can provide up to 41%, 25%, 35%, 32%, and 45 mV improvements of
${R}_{\text {WL}}$
,
${C}_{\text {BL}}$
,
${C}_{\text {WL}}$
, read speed, and write margin, respectively, compared to sequential and monolithic counterparts. Moreover, it also exhibits 77% energy–delay–area product enhancement compared to 14-Å-compatible nanosheet technology at the macro level (128-MB cache). These compelling results motivate further research and development of the process flow for hybrid CFET devices in SRAM technology in the future.