Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family whose energy efficiency approaches theoretical limits. Because AQFP logic gates depend on a polyphase excitation current to perform their computation, gate fanins must arrive at the appropriate excitation phase. Such a technology constraint has conventionally been treated by inserting buffers to balance shorter paths. However, path-balancing buffers account for a large portion of the circuit area, limiting the scalability of AQFP circuits. In this article, we examine the necessity of AQFP design constraints and propose a more relaxed set of constraints, which still guarantees the correct operation of AQFP sequential circuits. In particular, we propose to consider phase alignment instead of path balancing. Experimental results show that adopting the relaxed constraints reduces
$73 \%$
of buffers on average, and up to
$90 \%$
in some particularly-imbalanced benchmarks.