A Cost-efficient Hardware Accelerator Design for 2D Sliding Discrete Fourier Transform

This work presents a cost-efficient hardware architecture design of 2-D sliding discrete Fourier transform (SDFT). The proposed design requires the lowest eight real adders and six real multipliers in hardware resource, compared with Park’s method reduced by 11.1% and 25%, respectively. In the FPGA implementation, the proposed hardware accelerator is operated at 47.47 MHz, and then it is very suitable for time-frequency analysis in real time.