Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications

This paper proposes a design methodology and its hardware design of fast 3D-sorter engine in successive cancellation list (SCL) for 5G applications. Our hardware only requires fewer comparators as compared to the popular sorters, such as the odd-even sorter and Bitonic sorter. Meanwhile, the fast 3D-sorter engine has less computing time, owning the fast-computing feature for 5G demands. Our proposed work only occupies 7243.3 um
²
after synthesized with TSMC 40-nm CMOS technology. In comparison, our circuit outperforms the odd-even sorter and Bitonic sorter by 2.84 and 1.64 times, respectively, in terms of operating speed.