ESD-capability Study of High-voltage nLDMOSs with out the Drift Region DPW Effect

In this paper, a 0.18μm high voltage BCD process is used to design octagonal Lateral-diffused MOSFET(LDMOS), with a modified width of the DPW layer in the drift region. The width of the DPW layer of the reference device is designed to be 36µm, and the DPW layer is designed to be reduced by 12µm each time in the direction of the drain terminal. It is found that with the reduction of DPW layer, the trigger voltage (Vt1) increases from 58.805 (V) to 99.8 (V) when the DPW layer is 24µm (DPW24), an increase of 69.7 %; and the secondary breakdown current (It2) increases from 2.067 (A) to 4.486 (A) when the DPW layer is completely removed (DPW00), an increase of 117%. Finally, the best FOM value from the TLP test data was found to be the DPW00 device.