FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS

Error detection and correction techniques are conventionally employed in resilient systems to eliminate timing margins preserved in ICs. However, existing technologies still pose a significant overhead for resiliency or have limitations at near-threshold voltages. This brief presents a low-cost and wide-range timing management scheme FLC-EDC based on resampling. A novel 8-transistor timing detector (8T-TD) with a fast response time of 12.35ps (only 30.3% of 24T DFF’s) at TT, 0.9V, 25°C is proposed, which operates stably across a wide voltage range from 0.29V to 1.1V. Besides, the detection range is extended to a multi-timing detector (multi-TD) with the proposed timing collector, which significantly reduces the power and latency while reducing circuit stages. A compact error correction circuit based on a new mechanism is proposed, which postpones the rising edge of the clock and performs timing recovery through flip-flops resampling. Implemented on a 28nm CMOS neural network accelerator chip across 0.45V−1.1V, it achieves 34.6%/48.7% power reduction and 43.8%/253.4% frequency gain at the super-/near-threshold (0.9V/0.55V) at the cost of 3.27% area overhead. This scheme eliminates almost all timing margins, which effectively saves energy and increases energy efficiency.