Using Genetic Algorithm and Simulated Annealing with Memory to Solve Layout Synthesis Problem for GaAs MMIC

A GaAs microwave monolithic integrated circuit (MMIC) layout synthesis technique is presented. Evolutionary algorithms and simulated annealing-like algorithms are used in the suggested technique. A graph is used to represent circuit elements. Using genetic algorithm allow us to get global placement. Using first guess (pattern) allow us to reduce population size by 5 times, which lead to reduce synthesis time, and raise the probability to get feasible layout. Breadth-first search and depth-first search algorithms are used to obtain the pattern. Detailed placement is based on random refinement and simulated annealing with memory. Using detailed placement allows us to improve by 3 times solution obtained by genetic algorithm in terms of fitness function values. A * search algorithm is used to route solution. Von Neuman neighborhood and turning penalty are used to obtain tracing line with minimal bend counts. Suggested technique is validated with synthesis of 0.5-20 GHz 2 dB digital step attenuator section. Synthesized solution has 0.5 dB attenuation error, and met the requirements to reference state insertion loss and phase error.