iSynth - An open-source, technology independent, logic synthesis tool

Logic synthesis is an extremely important step in the VLSI chip design. Register Transfer Level (RTL) code is translated to logic gates in this step. These gates are manufactured on silicon at the end to get the final silicon. There are plenty of Electronic Design Automation (EDA) [2] tools available in the ecosystem for synthesis. But all of them need technology library from fabrication factories. It is not easy to get those library files for students and researchers for independent research. And they are extremely expensive. While the tech libraries are must for accurate results, a lot of design analysis can be done without them. This analysis can reveal a lot of issues early in the design without spending a lot. Technology independent synthesis tool [5] is the gateway for that. No one else has tried to develop a synthesis tool before using Icarus Verilog (iVerilog) extension framework. The novelty of this approach is that the Verilog compiler remains outside the tool. So, the tool remains light and does not carry the heavy compiler with it. Icarus Verilog, popularly known as iVerilog, is an established open-source mixed language compiler-simulator-synthesis framework [1]. It is covered by GPL. It has wonderful application programming interface (API) which can be used to create extension programs of iVerilog. We had used this extension capability to develop another tool in past - iLint [3]. This time we have developed the new synthesis tool. This tool is supposed to work with any version of iVerilog. We have tested the tool with iVerilog version 10, 11, 12 and 13 extensively and found to be working fine with these versions. The EDA tools are absolutely must in the field of VLSI design. There are many companies which develop EDA tools, but they are extremely costly. Open-source EDA tools plays a vital role in this area. In this paper we have described such a tool, which we have developed and named it - iSynth.