A 2bit/stage Reusability based methodology for designing 8-bit Binary Search ADC

This paper briefs a design of binary search (BS) analog-to-digital converter (ADC) using only N-2 comparators for N-bit resolution. The proposed design used efficient circuit design approach and reusability concept while designing the data converters. The post layout simulation done on UMC 180 nm CMOS technology using Cadence Spectre showed 21.1 mW of power-dissipation, 0.06 mm
²
of chip area, 7.5ns of conversion time and achieves 1 pJ/step-conversion Walden Figure of Merit (FOM). The proposed design is suitable for RFID and in SOC-applications.