A 12-Bit 125MSps Binary-Scaled Redundant SAR ADC with Partial Split Capacitor DAC

This paper introduces a 12-bit high-speed successive approximation register analog-to-digital converter (SAR ADC) 28nm CMOS process. Several techniques are proposed to improve analog-to-digital converter (ADC) performance. The binary scaling redundancy technique proposed in this paper can suppress the settling error of capacitor digital-to-analog converter (DAC) without sacrificing the resolution, thus reducing the settling time. Partial splitting capacitance technology can improve the conversion speed, and the dynamic offset can be reduced without the common mode voltage (Vcm) phase when the DAC is reset. In addition, the reference scaling binary method can exponentially reduce the number of unit capacitors, reduce power consumption and improve conversion speed without sacrificing accuracy. The ADC achieves an SFDR of 87.66dB and 11.68-bit ENOB with Nyquist input consuming 7.02mW at 0.9V supply, resulting in a Figure of merit (FoM) of 17.12fJ/conversion step.