A 60GHz 6-bit Digital-Step Attenuator with Low Phase Variations and Amplitude in 40-nm CMOS Technology

This paper designs a 6-bit digital attenuator that operates at 60GHz millimeter wave based on the TSMC 40nm CMOS process. The attenuation range is 0-31.5dB with a step of 0.5dB. The attenuator is composed of cascaded bridge- T,pi and improved- T structures, and an inductive compensation struc-ture is added to reduce additional phase shift. Interstage matching is designed to reduce the load effect between stages. By rea-sonably selecting the parameter model and topology, optimizing the layout design, the circuit performance is achieved and the simulation results are as follows: Within the range of 26-64GHz, RMS attenuation error <0.5dB, RMS additional phase shift <2.7°, insertion loss at 60GHz is 6.75dB, attenuation error is 0.15dB, 1dB gain compression point is 11.54dBm.