Design of A Fast Transient Response Capacitor-Less LDO with Dual Loop

This paper presents a fast transient response low- dropout regulator (LDO) with enhanced slew rate and no off-chip capacitor for system-on-chip (SOC) applications. The LDO regulator uses a combination of a folded-cascode operational amplifier and a transient-enhanced circuit to drive the PMOS pass element. The transient enhanced circuit can improve the slew rate of power element. The introduction of a dual-loop feedback loop architecture can further improve transient response. The proposed LDO is simulated based on SK 0.1S$\mu$m standard CMOS process. The result shows that when the input voltage is 2.1V, the output voltage is 1.SV, and the quiescent current is 37$\mu$A. Loop stability can be maintained with a load capacitance of only 10 pF and a maximum load of 50 mA. When the load current changes from 1mA to 50mA within 10ns, the undershoot and overshoot response times are 98ps and 97ps, respectively, where the best 0.075 ps FOM is achieved.