Low Trigger-Voltage Design of SCR Structure with Power-Rail ESD Clamp Circuit Network for On-Chip ESD Protection

In this paper, a novel method of deep reducing triggering voltage for silicon controlled rectifier(SCR) with detection circuit has been proposed and verified under a 0.25-μm 5-V Bipolar-CMOS-DMOS (BCD, Complementary and Double-diffused Metal Oxide Semiconductor) process. Its ESD performance is predicted and confirmed through two-dimensional device simulations and Transmission Line Pulse (TLP) test results. From measured results, this Zener diode triggering SCR with a positive injection doping (P+) Trigger Spot (ZDTSCR_P+) decreases trigger voltage from 32.39 V to 7. S2V and increases its holding voltage from 3.12 V to 6.62 V compared with conventional SCR. The ZDTSCRP+ features a narrow ESD window of low triggering and high holding voltage along with fast respond speed, which submits a robust and latch-up-immune scenario for power-rail ESD clamp circuit with SCR.