Essential Steps to Enable Analyzing Effective Resistance of ESD Paths-PG Routing Network Pruning and Resistance Contribution by Layer

Electrostatic Discharge (ESD) compliant interconnects are critical to protect internal circuitry. Full chip dynamic simulation can’t be a practical solution now, the compliance is analyzed in static points-to-points effective resistance (P2PR) and current density of interconnects along as-designed ESD paths. This paper focuses on P2PR. Performing ESD paths P2PR measurements on full chip are performance challenging, analyzing ESD paths P2PR incompliance are very complex too. This paper introduces two essential steps to make ESD paths P2PR measurement & incompliance analysis feasible on full chip production design flow. They are Power& Ground routing networks pruning in graph theory assisted by manufacturing data, and a reliable method to breakdown lumped P2PR value into resistance contribution by layer for incompliance analysis to help layout fix.