The Effect of Sige Siconi Pre-Clean Time On Planner Logic Device Performance Study

In this paper, different SiCoNi pre-cleaning time before the SiGe epitaxial growth process has been tried, and the effect of the Idsat and performance of the integrated SiGe (full-SiGe) and partial SiGe (par-SiGe) device was studied on a 28 nm planar logic device. The results showed that the Idsat of the core device nominal full-SiGe increases with SiGe pre-cleaning time, while that par-SiGe is just the opposite. The performance of the Core device nominal PMOS full-SiGe device got a significant improvement of more than 10% during the SiGe SiCoNi pre-cleaning time increased by around 20 seconds from upper and lower limits in our experiments on the 28 nm HKMG platform. Nevertheless, the performance of the PMOS par-SiGe was kept the same for increased pre-cleaning time.