A Study of Parasitic Capacitance Using Different Bit Line Spacer Integration Schemes in Advanced DRAM

In this study, we evaluate parasitic capacitance between the node contact (NC) and the bit-line (BL) in advanced dynamic random-access memory (DRAM) devices. Process modeling was used to analyze capacitance performance under different integration approaches. The results indicated that bit-line contact (BLC) along with bit-line pitch walking (BL PW) have strong impact on DRAM parasitic capacitance. The use of both low-k spacers and airgap spacers in the integration scheme helped to reduce parasitic capacitance. Our study showed that the average improvement was 16.5% with low k spacer and 31.3% with airgap spacer, respectively.