Influence of Interfacial Layers and High-k Post Dielectric Annealing On the Characteristics of MOS Devices

In this paper, investigation of the effects of Post Dielectric Annealing (PDA) and Interfacial Layers (IL) on the characteristics of Metal-Oxide-Semiconductor (MOS) devices. Based on the traditional MOS fabrication process, the PDA method provides a solution to the problem of large interface trap density (D
it
) after direct deposition of HfO
2
medium, and successfully reduces D
it
by about 78%. At the same time, compare the interface state and electrical characteristics of various IL layer deposition methods. The results showed that the Atomic Layer Deposition (ALD) method reduced D
it
by nearly 60% over the thermal oxidation method. And the positive shift of the flat band voltage (V
fb
) was increased by about 150 m. In addition, analyze the relationship between the change of V
fb
and the internal charge of the dielectric layer is analyzed, it is found that annealing and IL layer dielectric deposition methods change V
fb
by affecting the interface defect charge (Q
it
) and oxide defect charge (Q
ot
). In this work, the results provide a guidance for the interface optimization of advanced devices.