Cell Structure and Process Integration of a Novel 2T0C Technology for High-Density Dram Application

A new DRAM 2T0C cell is introduced to resolve those special issues for traditional 2T0C DRAM. In this technology, the read transistor holds dual gates. The data is stored in one gate of read transistor, and the other gate is used to control read operation. By writing different-level voltages into storage gate, the read transistor will have different threshold voltages by using the other gate as control gate. Compared with 1T1C DRAM, read operation in this new technology is non-destructive and therefore no explicit capacitor is required. Low leakage is essential for write transistor to obtain long data retention time. A few cell structures of this new 2T0C technology are discussed for high-density DRAM application, and challenges of process integration is also analyzed.