Study of the Formation of Copper Void Defect and Process Optimization For Reduction In Dual Damascene Process

Copper void defect issue is becoming more sensitive for the quality of backend interconnect metals with the downscaling of the semiconductor devices. There are many reasons for the formation of copper void. In this paper, the q-time between ECP to CMP, and the influence of different ECP additives, different ECP anneal times and different CMP slurry were studied to reduce copper void defect. With the q-time between ECP to CMP longer, the Cu void performance is worse for the self-annealing effect. And the copper void defect performance is obviously different when different ECP additives were used. As the purity is higher of Cu ECP additive, the copper void performance is better. In addition, the ECP annealing time longer, the defect condition is becoming worse. These conclusions are effective to reduce the copper void defect.