Verification of 100Gb/s Data-Rate Transceiving through Silicon-Photonic Module in an FPGA Platform

This study conducts research on the performance of NRZ 100Gb/s modulation, as well as its scalability to PAM4 400Gb/s and 800Gb/s data-rate. The FPGA verification platform consists of a CMOS SerDes, an InfiniBand Extended Data Rate (IB EDR) module, a 4-lane QSFP28 compliance board, and a loop-back on-board optics (OBO) 100G Evaluation Board, with electrical/optical I/O assembly or silicon-photonic (Si-Ph) chip module. The FPGA platform follows the Common Electrical I/O (CEI) standard. For high-speed data-rate of 100 Gbps through 4$\times$ 25G SerDes TX/RX, the eye diagrams and the bit error rate (BER), of Si-Ph loop-back and fiber-Si-Ph loop-back, are measured respectively. The results lead to discussions on the applicability the newest Compute Express Link (CXL) 3.0 in FPGA verification platform, which supports NRZ and PAM4 modulations. It is also suitable to evaluate essential characteristics and applications, such as the delay and interconnect concerns in co-packaged optics (CPO) technology, of IP integration and chiplet packaging.