A Novel Schematic Placement and Routing Algorithm for FPGAs

As an essential part of FPGA design tools, schematic diagrams must be convenient, fast, readable, and regular for designers to view and modify the circuits. However, placement and routing algorithms limit the the time and effect of generating the diagrams. The existing tools mainly adopt heuristic algorithms, which have a high time cost, or coarse-grained sorting algorithms with poor solution effects. To address these issues, we propose a novel schematic placement and routing algorithm for FPGAs. Aiming at the instability and high timing cost of traditional algorithms for placement and routing, the proposed algorithm (1) adopts heuristic selection for initial value to solve the instability of traditional coarse-grained sorting, and (2) adds score mechanism for fast sorting, and (3) utilizes the backtracking and error correction mechanism to decrease the accumulated errors. Compared with the traditional heuristic algorithm, its complexity is only O(nlogn). The evaluation on the linux system shows that most cases have appropriate crosspoints and less than 10s running time, which demonstrates that our algorithm acquire the balance of the solution result of coarse-grained sorting and the time cost of the heuristic algorithm.