Design Space Exploration of Multi-Stage Op Amps by Symbolic Modeling and gm/ID Sampling

Design of multi-stage CMOS operational amplifiers (Op Amps) faces unknown design spaces. Designers are often unclear about whether a manually sized circuit has achieved a good tradeoff between multiple design targets and whether other better sizing candidates exit. This paper proposes a design space exploration method for the class of multi-stage Op Amps based on symbolic circuit modeling and gm/ID design variable sampling. This method is easy to implement based on a symbolic circuit modeling tool. Experiment conducted on a three-stage op amp has demonstrated that multiple feasible sizing solutions with explicit performance tradeoffs can be obtained simultaneously.