A Synthesis Method for Verilog Case Statement Using Mux-and-Inverter Graph

Crossbar architectures are widely used in high-performance network switches, such as connecting PEs in multiprocessor systems. The crossbar is usually synthesized by CASE statements in Verilog, and its delay largely affects the performance of the whole design. We proposed a multi-strategy synthesis method exclusively for CASE statements. Based on mux-and-inverter graph (MAIG), this method simplifies selection logic using the Boolean characteristic. Experimental result shows that this method could bring 4.30% less area and 16.3% less delay than Yosys.