Learning a Provably Good Wirelength Model for Analytical Placement

Placement is one of the most critical design stages for very large-scale integrated (VLSI) circuits. Modern VLSI placers usually adopt the analytical placement framework, which formulates placement into a non-linear optimization problem. A key ingredient of analytical placers is the wirelength model. Previous works propose various models to approximate the half-perimeter wirelength (HPWL). However, these models rely on human experiences and may not be fully optimized on realworld designs. In this work, we propose a novel data-driven parameterized wirelength model, which learns the best configuration from placement instances in the training set via Bayesian optimization. Our model is effective and efficient, together with a provable upper bound of the generalization gap. Therefore, the model can generalize to testing data that is unseen during training. Experiments show that our model improves HPWL on average by 1.9% compared with the classic weighted average model on ISPD-2005 benchmarks using DREAMPlace.