Accurate Timing Path Delay Learning Using Feature Enhancer with Effective Capacitance

Accurate timing path delay calculation is a critical technique during the process of chip design. For widely used path delay calculation methods, cell delay is captured from look-up table (LUT) and wire delay is calculated by classical Elmore model, which can be considered as first-order- moment matching approximation, efficient and easy to use but ignoring the resistive shielding. The wire delay calculated by commercial static timing analysis (STA) tools is still opaque and such lower-order moments delay have large errors compared with commercial STA tool. In this work, to address these limitations, we propose a learning-based timing path delay and wire delay prediction model with feature enhancer. Our model utilize the feature enhancer to calculate the wire delays with different classical wire delay metrics not only Elmore model, Delay with two Moments (D2M) model but also Effective Capacitance Metric (ECM) model and Modified D2M (MD2M) model, which captures resistive shielding by modeling the load capacitance with effective capacitance instead of total capacitance. Furthermore, an effective trick about label is setting the ratio of path delay from commercial tool to traditional method as label, which is critical for improving generalization and accelerating the convergence rate. Experimental results on multi-corner wire delay prediction demonstrate that our model using feature enhancer with effective capacitance achieves an average rRMSE values of 0.4% for trained designs and 3.3 % for unseen test designs.