HDLcs1.0: A Compiler and Simulator Framework for Hardware Description Language

With the increasing scale of integrated circuits, the design of processor chips is highly dependent on EDA tools. Verilog-oriented HDL (Hardware Description Language) processing tools are the key software for front-end design. Apart from commercial EDA tools, open source tools still have room for improvement and optimization. Based on open source software, the required key tools can be further expanded, especially at the gate-level circuit level. This paper presents a compiler and simulator framework HDLcs1.0 for Verilog HDL. Based on LLVM technology and simulator design, we initially established a feasibility framework, which can meet the needs of RTL simulation.