System Static Timing Analysis Method Based on Hierarchization

Static timing analysis (STA) is a technology used to verify the timing of digital design. In the simulation and verification of VLSI, multiple FPGA chips work together. To obtain the timing performance of the system, it is necessary to establish a timing analysis model from the perspective of multiple FPGA systems. And STA will be called many times to verify the circuit timing in the logic synthesis, placement and routing stages of the design, which makes the development of fast system level STA algorithm a key. In this paper, a multi-core accelerated system STA algorithm is implemented. Based on the logical hierarchy on the timing path, the delay on the path is solved in parallel by using the non-correlation of the data at the same hierarchy, and achieves 3.9 times of parallel speed-up on 8 cores of the CPU.