Demystifying the Influence of Channel Components on Signal Integrity (SI) Margin

Huge demand for functionality, performance and bandwidth has increased the complexity of high-speed designs. Different channel components like central processing unit (CPU) package, add-in-card (AIC) package, printed circuit board (PCB) trace or transmission line, via, and connector parasitics impact eye margins differently. In this paper, peripheral component interconnect express (PCIe) interface is used to demonstrate the same. While PCIe Gen 5 loss budget is 36 dB at 16 GHz Nyquist, depending on these channel components, a design can go above or below this loss requirement. Sensitivity analysis of variations in CPU package, AIC package, PCB transmission lines, and connector in a high-speed channel is studied along with its impact on the overall channel margin.