Design a Hardware of Image Stitching Using LBP Algorithm

Image stitching algorithms are often used in real life and are mostly handled by software. The proposed method is a hardware design level image processing method using a local binary pattern. To solve the background matching problem during stitching, the proposed method is used instead of the existing stitching algorithm. Designed with Verilog HDL, it minimizes multipliers to reduce resource consumption. It applies parallel processing and pipeline architecture to increase processing speed. The goal is to use the proposed algorithm to design hardware with similar accuracy to the existing algorithm.