FPGA-based tunable Keccak core

Nowadays’ great emphasis on data security has led to a great need for hardware accelerated cryptograhic algorithms to cope with the high communication bandwidth demand. These hardware accelerators need to be highly tunable in order to support multiple operation modes for different security applications. In this paper, a Field Programmable Gate Array (FPGA)-based design and implementation of a tunable Keccak core is presented. The Keccak core’s performance and security parameters are configurable in the sense that bitrate, capacity, and the number of rounds can be user-specified with an extendable output length. Keccak’s sponge construction is exploited to enable different modes of operation. This level of flexibility makes the core a suitable fit for a large range of security requirements and applications. The implemented core can be operated as a sponge-based Pseudo Random Number Generation (PRNG). The design was implemented in VHDL (VHSCI Hardware Description Language) targeting a low-cost IntelFPGA Cyclone-V. The core achieved the following maximum throughput figures of: 11, 8.4, and 5.81Gbps for the three Secure Hash Algorithm-3 (SHA-3) variants 256, 384, and 512-bit respectively, while occupying only 8% of the FPGA’s area. The random sequences generated by the sponge-based PRNG successfully passed the National Institute of Standards and Technology (NIST) test suite. This paper demonstrated respectable area/performance results compared to other studies in literature.