Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs

Multipliers are one of the most power-hungry arithmetic circuits on hardware neural network accelerators on field programmable gate array (FPGA). In this letter, design of hardware-efficient softcore multipliers using adaptive logic modules (ALM) is presented. Two partial products (PP) are added using a Karnaugh map (Kmap) to fit on one Intel FPGA ALM in such a way that two consecutive rows of Booth PP matrix are merged. 29.26% energy savings are observed by AR-44 compared to the exact multiplier with a drop of 0.63% accuracy on VGG16 convolutional neural network.