A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os

Wide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking [through-silicon via (TSV)], silicon interposer in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip interface, handle a large amount of data in the server and artificial intelligence (AI) applications. With a large number of IOs, power consumption becomes a huge burden. This article presents a novel charge recycling (CR) logic with >20% power reduction under random data streaming. The presented generic CR technique is applicable to both TSV and transmission line (T-Line) link IOs. The CR logic is implemented on two silicon dies where the single-channel CR (CR1) uses a storage capacitor to recycle charge at each data transition and multi-channel CR (CR2/4/8) replenishes the charge between multiple channels during the opposite transitions. Fabricated in a 40-nm 1P8M standard CMOS, the TSV link (2.56 Gb/s) and the T-Line link (5.12 Gb/s) save energy up to 32.2% and 47%, respectively, under periodic data transmission and up to >20% under pseudo-random binary sequence (PRBS). The eye diagrams and the bit error rate (BER) show that signal integrity is maintained when compared with conventional data links.