Design Optimization and Performance Analysis of a Three-Phase Three-Level MVDC Bidirectional Isolator using Series-Connected 10kV SiC MOSFETs and 10kV SiC JBS diodes

This research article presents a thorough investi- gation of the 3 Level - 3 Phase (3L-3P) Neutral Point Clamped (NPC) Dual Active Bridge (DAB) topology for designing Medium Voltage (MV) DC isolators. An equivalent circuit model is utilized to provide a detailed analysis of the switching transition at specific operating points, including α = 60°, 0 < ϕ < 90° (ϕ ≠ 60°) α = 60°, ϕ = 60°. These operating points not only ensure optimal performance but also minimize the Common Mode (CM) current injected into the operating environment. The article also employs the model to evaluate the minimum current required for Zero Voltage Switching (ZVS) operation, snubber current during turn transition, and the loss in the snubber resistor. Furthermore, the article proposes a dynamic voltage balancing algorithm that significantly reduces DC offset by 80% and switching losses by 50% through precise turn-off Vds mismatch across MOSFETs and Diodes within a specified limit of 100V. The accuracy of the model used in the proposed algorithm is validated through experimental turn-off waveforms of SiC MOSFET at 1.75kV. The article introduces experimental test benches to examine the impact of base plate capacitance (C
bs
) on the voltage mismatch and snubber losses in the 3L pole, providing valuable insights into the behavior of the topology under various conditions. The experiments are conducted up to 6kV DC bus voltage, and the snubber loss and dynamic voltage mismatch across series connected MOSFETs and diodes are evaluated and validated through the theoretical model.