SiC MOSFET Crosstalk Modelling with Suppression Considering Impacts of dv/dt and di/dt

Compared to Si IGBTs, SiC MOSFETs can reduce switching losses, achieve higher switching frequencies and enable smaller converter size. However, due to the high dv/dt of SiC MOSFETs, certain topologies, such as two SiC MOSFETs in a phase-leg configuration, are highly sensitive to crosstalk, which can slow down switching speed and even reduce gate oxide’s lifetime. In this paper, an accurate model of crosstalk is established by considering the impacts of both dv/dt and di/dt in the power loop. The proposed model can simulate the gate-source voltage on bare die of SiC MOSFETs, allowing for a more accurate evaluation of the impact of crosstalk. Model verification is implemented using a double pulse test (DPT) platform and a gate driver with active miller clamp technology. Key parameters of the model are extracted from both 3D simulation models and measurement experiments. The DPT waveform of power loop is used as the excitation source in the simulation, and the simulated gate-source waveform shows good agreement with the experimental waveform. Based on the model, parameter sensitivity analysis is performed, and suggestions for improving crosstalk suppression are proposed.