A Formal Design of Parallel CRC Circuit

Cyclic Redundancy Codes (CRCs) are useful to detect burst errors in storage and communications systems. This paper analyzes the theoretical principle of CRC and the parallel CRC structure. Besides, this paper proposes a design method for the parallel CRC, which can generate parallel CRC circuits with different parallel bit width, different CRC generating polynomial, and different input data length. The FPGA performance (LUT consumption and max frequency) of our approach is comparable to the state-of-art parallel CRC method. This paper may be useful for parallel CRC circuit design.