Three-stage Split Capacitor Array with Redundancy for an 18 bit SAR ADC

Capacitor array is being a limiting factor in improving the accuracy of SAR ADCs. This study introduces a capacitor array that is suitable for an 18-bit SAR ADC. The proposed capacitor array employs a three-stage technique to reduce area requirements and matching constraints. The design incorporates reusing of capacitor to reduce the required capacitance and a split-capacitor configuration for V
CM-free
sampling with lower power consumption. Additionally, the design features redundant bits and a direct digital domain calibration method for weight coefficient fitting. Simulation results demonstrate 95.7 dB SNDR, 101.4 dB SFDR, and 14.51 bit ENOB.