FPGA based Power Efficient Approximate 4:2 Compressor for Multimedia Applications

Approximate computing plays a crucial part in error resilent and multimedia applications. This study presents the design and analysis of a 4:2 compressor that employs a Dadda multiplier to reduce output power and inaccuracy. The approximate compressors are utilized to design 8*8, 16*16,32*32 multipliers. The goal of this work is to develop a compressor with low latency, low power consumption, and fewer product stages. By reducing the number of transistors and gates the low latency compressors used to serve as multiplier design applications. The adders and product stages are to be considerable power consumption in multiplication process. The reduced compressors consume less power and it could be applicable for designers.