A High-precision Delay Locked Loop with Current Mismatch Calibration in 40nm CMOS

This paper proposes a calibration circuit to mitigate current mismatch of charge pump (CP) in delay locked loop (DLL), improving its static phase offset (SPO) performance greatly under process voltage and temperature (PVT) variations. By introducing a negative feedback loop including CP output, the proposed calibration circuit can achieve perfect current matching regardless of CP output voltage. To verify the effectiveness of the proposed method, a CP DLL with proposed calibration and current compensation is designed and compared to traditional one in 40nm CMOS process. The simulation results show that with the proposed current calibration, the DLL corresponding static phase offset is reduced to 0.095ps with a clock frequency of 100MHz, while that of the traditional one is 18.04ps. The power consumption of the proposed CP DLL is 5.24mW under 0.9V supply.