Efficient Bicubic Interpolation Architecture for RGB Image Data Stream

Super-resolution, which is applied to produce sharp and high-resolution images, has become an important research direction in the field of image processing. Interpolation-based super-resolution algorithms are widely used for hardware implementation. In this paper, an efficient super-resolution hardware architecture with an improved bicubic interpolation is proposed. First, the original algorithm is optimized by changing the algorithm order, and a three-stage pipeline circuit is implemented. Then, the hardware architecture, including a 4-bit shift register, two sliding windows and a controller, is proposed and successfully implemented on Xilinx Zynq 7020 platform, achieving about $96\times$ speedup compared with Intel i5 with the same image quality. Compared with other related works, the proposed bicubic compute module achieves a higher image quality while consuming similar hardware resources, especially the number of DSPs and Adders decrease greatly, which are 19 and 29, respectively.