A Partitioning Algorithm Based-on Vertex-degree of Undirected Graph for VLSI Circuit Simulations

A gate-level partitioning algorithm based on vertex-degree of undirected graph is proposed for parallel simulation of very large-scale integrate (VLSI) circuit in this paper. Both the inner-and outer vertex-degrees of the undirected graph are used for VLSI circuits division, then the interconnections between the partition modules are then minimized. Furthermore, clustering using adjacency relation between the partitions is completed for balanced loadings among modules. Performances of the proposed and conventional partition algorithms, including the Deep-First-Search(i.e. DFS) algorithm and Metis partition tool, were evaluated in terms of the minimum cut set, module loading balance and partition time consumption, respectively. Algorithm implementations of 66- gates to 5743- gates circuits, show that the proposed algorithm renders a decrease of the minimum edge cut number by 51.1% and 5.9 %, compared with the DFS algorithm and the Metis partition, respectively. In addition, the average time consumption of the proposed algorithm is reduced by 44.9%.