Multi-FPGA Interconnect Design for Heterogeneous Computing

This paper presents a Multi-FPGA interconnect design for heterogeneous computing that extends the concept of on-chip networks to inter-chip interconnection. The design includes lightweight routers, scalable mesh networking, and 10GB MAC+PHY as the underlying protocol of transmission. DMA is used to exchange data between the ARM processor and FPGA inside the node to ensure dynamic traffic transmission performance. Moreover, a global flow control strategy is proposed to ensure load balancing during transmission and avoid data loss.