FPGA Implementation for Multiple CFAR Algorithms

While analyzing radar signals, the constant false alarm rate (CFAR) method is crucial for detecting targets. Target detection has to be very accurate, particularly in nonhomogeneous situations like multi-target or clutter edge conditions. There are several types of CFAR algorithms, which are used in radar applications that need to identify targets in real time. These algorithms require a lot of computational time. In this research, a programmable hardware architecture has been described for the implementation of multiple CFAR algorithms. The implementation will have the ability to swap between several CFAR algorithms: average, max, min, and order statistics. The proposed implementation of CFAR algorithms is tested using adaptive processing of noisy signals for target recognition in real time. Variants of CFAR algorithms are built within one architecture, which is created to handle parallel processing. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. The Xilinx Vivado toolset’s synthesis, post-place and route are to find the best point to linearly speedup processing and resource usage.