Emulation: Accelerating Simulation for Rapid Verification of Modern Processor-based Subsystems

Verification of a design before silicon fabrication is a crucial step in the semiconductor design process. Before chip manufacture begins, every bug must be identified and addressed. As the complexity of a chip rises, more time is needed to establish appropriate testcases and testbenches. Recent studies indicate that the verification process consumes around 56% of the development time for an ASIC project. In addition to the time spent developing verification environments, a significant amount of time is "wasted" on slow verification platforms (typically simulators working at a frequency of few hertz). In case of large testcases, the duration of the runs has grown alarmingly (several hours or even days). As a result, numerous emulation techniques have been developed recently. However, only a few solutions could demonstrate success in balancing the design, hardware, and communication costs. To minimize time-to-market, it is important to notably increase verification flow speed. In this research, the Transaction Based Acceleration (TBA) technique is proposed for modern processor subsystems. TBA is a type of emulation technique that employs a shared testbed for both simulation and emulation while determining which testbench components can be shifted to the emulator side. The testbench is separated into two sections: the synthesizable Bus Functional Module will migrate to the Emulator side, while the Proxy Testbench will remain on the Simulator side. The Design Under Test (DUT) operates on the emulator, where we try to shift the maximum functionality of the Testbench. The objective is to showcase the effectiveness of TBA in rapid verification of any Processor Subsystem. In this paper, we have brought up the technique for ARM Cortex M-33 and Ibex RISC-V based processor subsystems. Xcelium Simulator and Palladium Z1 Hardware Emulator from Cadence are used. Maximum speed increase obtained with ARM Cortex M-33 is 107.84x where Simulation for a testcase took 3 hours, 10 minutes, 31 seconds; however, our proposed technique required only 1 minute, 46 seconds, resulting in a time reduction of 99.07 percent. In case of Ibex RISC-V based subsystem, maximum speed increase obtained is 132.25x where Simulation for a testcase took 3 hours, 44 minutes, 49 seconds, our proposed technique takes 1 minute, 42 seconds, resulting in a time reduction of 99.24 percent.