Hardened Processor Architecture

Processors for terrestrial applications are protected by Earth's atmosphere and magnetic field, so the probability of single event effects (SEE) is significantly lower. Shrinking of the technology nodes allows higher operational frequency and performance, but their susceptibility to SEE is increasing. Nowadays satellites and safety critical automotive applications require more and more computational power. The hardening by design has been implemented mainly by redundancy of the whole cores. The consequences are lower frequency, larger area, and higher power consumption. We propose a novel hardening technique, which enables high frequency operation and doesn't cause large power consumption and area overhead. The protection is based redundancy and separation of the pipeline into two main sections. It provides a fast detection of faults, simple recovery by flush of the pipeline, and allows a large prediction unit to be unprotected. The whole protection scheme can be implemented at the Register Transfer Level. We present the protection scheme at the core with RISC-V instruction set. Simulations confirm the protection can handle the injected faults. Synthesis shows, the protection lowers the maximum frequency by only about 4.7%. The area increase is only about 118% and can be even lower.