A New Continuous Time Offset and Gain Calibration Strategy for Open-loop Residue Amplifiers of ADC

A continuous-time offset cancellation and gain calibration strategy is proposed for open-loop residue amplifiers of pipeline ADC's. The strategy detects gain and offset error using a reliable technique and saves digital amounts of the signals which are resulted from the calibration loop. This allows data conversion to proceed without any interruption. The structure is shared between several RA stages in ADC, decreasing power consumption and area occupation. The strategy does not require extra circuits like replica residue amplifier or wide-bits digital processor for offset and gain-error correction. Utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input-referred offset is reduced to around 30
$\mu \mathrm{V}$
. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Proposed structure has been simulated using HSPICE software in 0.18 μm standard CMOS technology and results show that in 14-bit and 16-bit 200 MS/s Pipeline ADC, there are a 23dB improvement in SNR and 3.9 bit in ENOB.