3-D Modeling and FEA for MCM by APDL

In order to accurately analyze interconnect reliability for a complex multi-chip module (MCM), a highly integrated RF MCM for TDD base stations which is consisted with two Si switch chips and two GaAs low noise amplifiers is taken as an example here. ANSYS Parametric Design Language (APDL) is used to achieve the automatic 3-D modeling, and the temperature reliability can be predicted by finite element analysis (FEA). This is the first time to conduct interconnect reliability analysis for a MCM chip. This can provide the basis and guidance for interconnect reliability analysis and design of MCM chip. Meanwhile, the 3-D modeling is high-efficient in modeling time and memory.