HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor

This paper presents a detailed description of the design of a 64-bit RISC-V processor that implements the RISC-VISA using Verilog hardware descriptive language. The design is simulated using Xilinx 14.7 simulator. Unlike CISC ISA, which has a variable length ISA, the RISC-VISA is a fixed length ISA, making the design simpler. The primary objective of this paper is to achieve a four-core processor design. Each core is parallel and pipelined, following multicycle and stages. Control signals for each core are hardwired logic that operates through sequential circuits as the instruction cycle goes through various stages. However, the scheduling of cores is microprogrammed through a shell. The compiler plays a crucial role in the process of decoding instructions from higher-level language to assembly level. At the single-core level, the instruction cycle comprises five significant stages, with each stage subdivided into two cycles. This paper provides valuable insights into the design of a high-performance RISC-V processor with multiple cores, and the implementation of the processor using Verilog hardware descriptive language. The results of this study can be beneficial in the development of efficient and powerful processors for various computing applications.