Design and implementation of Kogge-stone, Sparse Kogge-stone and Spanning tree adder

Many Very Large Scale Integration (VLSI) circuits typically employ Parallel Prefix Adders (PPA). Power, size, and speed are the key constraints for designing an adder circuit because there is a trade-off between them. In-depth research is still being done on minimising the power delay and thus improving adder performance because the binary adder is an essential part of the majority of digital circuit designs, as well as Digital Signal Processors (DSP) and microchip knowledge path units. The Kogge-stone (KSA), Sparse Kogge-stone (SKS), and Spanning tree adders are examined in this research along with current adder designs. Their performances are compared in light of various design constraints to discover which adder performs the best among them.