Design and Implementation of an Arithmetic Unit with Reduced Switching Activity

Binary adders play a significant role in many high-performance systems, including those for digital signal processing, image processing, and multimedia processing. It is more challenging to build an appropriate binary adder for low power consumption, latency, energy efficiency, and silicon chip size. Since it can significantly lower the overall energy consumption of electronic systems, low power consumption is a crucial factor in the design of integrated circuits. The physical capacitance being switched directly affects the circuit's dynamic power consumption. In this paper, algorithm- based design is proposed to significantly lower gate Switching Activity (SA) of basic logic gates (AND, OR, and NOT) and as a result, power consumption is reduced. Comparatively, the NOT gate has a high switching activity. Utilizing the logic decomposition method, the suggested complete adder design reduces the quantity of NOT gates and the circuit's total SA values. The binary adder's dynamic power dissipation and circuit size are reduced as a result. This adder is implemented on two different complex adders. The design metrics are implemented on the Digilent Nexys 4 DDR Artix-7 FPGA and synthesized with the Xilinx Vivado v2019.1 compiler