Design Exploration of an Efficient Adder Architecture for High Performance Computing

For error-tolerant applications, approximate computing decreases design complexity while improving performance and power efficiency. In many applications, precision is not strictly required. The paper provides a new method for approximating the entire adder. In this paper, a 4-bit approximate ripple carry adder is proposed for low power consumption. The conventional ripple carry adder consists of 20 gates which consumes high power, whereas the proposed has only 8 gates thereby lowering the power consumption without much errors. Carry of the conventional full adder has been modified to decrease area complexity. The area, delay, and power consumption of approximate ripple carry adder is examined in this paper. Simulation results result in 10.90% power savings using the proposed approximate adder. The design metrics are simulated using Xilinx Vivado v2019.1 and implemented in Digilent Nexys 4DDR Artix-7 FPGA.